Conventional horizontal phase-locked loops (PLLs) for video decoders serve the purpose of locking the sampling clock (for clocking digital pixel information into the phase-locked loop) of an analog to digital converter (ADC) to the falling edge of the incoming horizontal sync of composite video information. This lock is required to generate a stable picture in the horizontal direction and position signals which identify the sync tip, back porch, the color burst, and the active video region of the composite video input. The analog video information enters an analog-to-digital converter which outputs digital pixel information. A pixel counter counts video information corresponding to pixels in what can be considered a horizontal scan line across a display monitor screen such as a cathode ray tube. The pixel counter starts with a count of zero and counts to a terminal count and then falls back to zero.
The PLL employs two modes of lock; a coarse lock and a fine lock. In the coarse lock mode the incoming horizontal sync pulse which is usually present during the blanking interval of each line associated with the video signal (for the purpose of being able to synchronize the scanning of the monitor with the scanning of the original image), is detected by a digital circuit. Based on the decode of the pixel counter, a coarse gate window (meaning a relatively wide time window in comparison with the narrow time window associated with the fine window discussed below) is enabled around the time the horizontal sync pulse is expected. If the sync does not occur within the gate window for a time corresponding to several consecutive video lines, then either the pixel counter is reset or a correction is made to the clock frequency of the video decoder system in order to move the window to the sync pulse. When the sync pulse falls within the fine lock window, then the fine lock mode is enabled.
A fine gate window is employed by the fine lock mode which enables a phase detector which calculates a phase error based upon the position of the edge of the sync pulse within a narrow window known as the fine window. This phase error is then filtered by a loop filter whose output is fed to a discrete time oscillator which adjusts the clock frequency to move the sync pulse so that its edge is centered in the fine window, thereby minimizing the phase error.
The sync detector detects the horizontal sync and outputs the phase error which represents its deviation from the desired lock position. It is highly desirable for the sync detector to work with non standard video and weak signal inputs. Non standard video is output by VCRs, DVD players, and video, for example. A VCR may produce a signal whose time base is unstable and depends upon its modes of operation which include normal play or trick mode (pause, fast forward, and rewind). The horizontal sync frequency may vary up to 5% from the nominal. Head switching can produce horizontal sync jumps up to 15 microseconds from its normal position before the vertical sync interval. During trick modes, the number of lines per frame may also vary by +/−6% and the vertical sync may change shape.
Copy protection, such as macrovision, is added to the video signal and presents additional problems with horizontal and color lock as well as automatic gain control (AGC) adjustment in the analog front end. Macrovision consists of distortions such as pseudo syncs, AGC pulses, color stripes, and sync height differences between the vertical blanking and active video intervals. Pseudo syncs can interfere with horizontal lock if they are misinterpreted as real syncs. Weak signals occur due to the reception of weak RF signals from a distant transmitter; they may also have a reduced sync amplitude caused by saturation of the RF antenna amplifier. Weak signals may also contain ghosts or echoes due to multipath reception caused by reflections of the RF off objects such as mountains, airplanes, and buildings.
Previous sync detectors consist of a separate coarse detector and a fine detector. The coarse detector detects the falling edge of sync in the filtered ADC output when it goes below a fixed trigger level. The fine detector generates a phase error based on the accumulation of, for example, 15 weighted pixels that fall within a narrow window. A limitation of having a separate coarse detector and fine detector is a non-uniform linear transfer function which produces an abrupt or sudden change in the phase detector characteristic when switching from a coarse mode to a fine mode resulting in horizontal jerkiness and/or oscillations in the picture. A normalization constant which is a function of the fixed trigger level is applied to the result in order to generate a zero crossing corresponding to the falling sync edge. The correct trigger level is critical to proper sync detection which, in turn, depends on AGC and offset adjustments in the analog front end to generate the correct levels for horizontal sync tip and back porch.
Other limitations of previous sync detectors include requiring synchronization to the input video signal and requiring automatic gain and offset adjustments in the analog front end. The video decoder must be fine locked to the input signal before the analog front end can adjust its gain and offset to achieve target sync height and back porch levels at the ADC output; the trigger level is set to the midpoint of these two levels. Therefore, the signal at the ADC output prior to lock must already be in the range where it can trigger sync detection. As a result, the range of input signal amplitude is limited over which lock can be achieved.
It is therefore desirable for the present invention to overcome the limitations and problems described above that are involved in a horizontal sync detector.